Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology - 2017 PROJECT TITLE :Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology - 2017ABSTRACT:Ternary content-addressable memory (TCAM)-based mostly search engines generally want a priority encoder (PE) to pick out the very best priority match entry for resolving the multiple match drawback due to the don't care (X) features of TCAM. In contemporary network security, TCAM-based search engines are widely employed in regular expression matching across multiple packets to safeguard against attacks, like by viruses and spam. However, the use of PE ends up in increased energy consumption for pattern updates and search operations. Instead of using PEs to work out the match, our answer may be a three-part search operation that utilizes the length info of the matched patterns to decide the longest pattern match knowledge. This paper proposes a promising memory technology referred to as priority-call in memory (PDM), that eliminates the need for PEs and removes restrictions on ordering, implying that patterns will be stored in an arbitrary order while not sorting their lengths. Moreover, we have a tendency to gift a sequential input-state (SIS) scheme to disable the mass of redundant search operations in state segments on the basis of an analysis distribution of hex signatures during a virus database. Experimental results demonstrate that the PDM-based technology can improve update energy consumption of nonvolatile TCAM (nvTCAM) search engines by thirty sixp.c-sixty seven%, because most of the energy in these search engines is used to reorder. By adopting the SIS-based methodology to avoid unnecessary search operations in a TCAM array, the search energy reduction is around sixty fourpercent of nvTCAM search engines. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest VLSI HSPICE MTech Projects High Performance Ternary Adder using CNTFET - 2017 Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders - 2017